There is a limit on the miniaturization of a plane area of the electrode pad for semiconductor devices, especially for a power device which requires a large current, because a diameter of a wire or a size of a ribbon to be connected to the electrode pad is preferably large in order to apply a large current. Accordingly, a so-called pad-on-element structure where an electrode pad is formed on an element is being considered (for example, see U.S. Pat. No. 5,773,899). Also, a structure that an electrode pad is connected to an under wire by using a plurality of vias, which does not provide the electrode pad over the element, is being considered for preventing a pad from cracking (for example, see Unexamined Japanese Patent Publication No. 2000-195896).
U.S. Pat. No. 5,773,899, which is a first conventional example, describes a structure as shown in FIG. 23 where first wire 18 is wire-bonded on an element. Regions of two wiring layers 12 and 16 where first wire 18 is connected configure a pad structure which is connected with almost the whole of wiring layers 12 and 16. This pad structure does not include an insulating film between two wiring layers 12 and 16, and thus adhesivity between wiring layers 12 and 16 is desirable. On the other hand, with respect to second wire 17, insulating film 13 is provided on almost an entire region between two wiring layers 12 and 16, and stress is relaxed by insulating film 13.
Also, Unexamined Japanese Patent Publication No. 2000-195896, which is a second conventional example, describes a structure as shown in FIG. 24 where, as a pad structure formed on substrate 51, wiring 54 is connected to pad 52 formed on wiring 54 by a plurality of vias 53. The strength of pad 52 is increased by being supported by a plurality of vias 53. This is a structure where a flattening process or the like is performed after a plurality of vias 53 are embedded in insulating film 55, and insulating film 55 is supposed to be an inorganic insulating film.